1. Field of the Invention
The present invention relates to a semiconductor memory device having an error correction function. The device can process both a soft error and a hard error by adding an error correction code (ECC) and redundant bits.
2. Description of the Related Art
A redundant technique is widely known which improves the yield of semiconductor memory devices. In the redundant technique, a redundant memory cell array storing correct data is added to a regular memory cell array. When a defective memory cell is selected to be read, the redundant memory cell is actually read in place of the defective memory cell, so that the correct data can be read. However, this redundant technique can be applied only to previously determined defective memory cells. That is, once defective memory cells are determined, other defective read data caused by hard errors or soft errors after the determination of the defective memory cells can not be corrected.
An increase in the capacity of a dynamic-type memory device easily causes the occurrence of soft errors by .alpha. rays. Whether the data read from the memory is correct or incorrect can be determined by means of parity checking. However, although the presence of an error bit may be determined by parity checking, the position (address) of the error bit cannot be determined, and accordingly, error correction cannot be performed. To determine the error bit and to make it correctable, an improved parity checking technique employing a parity-checking two-dimensional virtual matrix has conventionally been incorporated into a conventional semiconductor memory device (see, for example, Japanese Unexamined Patent Publication No. 57-152597, Inventor: Junzo Yamada et al, Applicant: NTT, Filing date: Mar. 17, 1981). This conventional semiconductor memory device employing the parity-checking two-dimensional virtual matrix, however, can correct only a single bit error, as later described in more detail. Further, since the redundant technique is not employed, it provides a low yield.
The above-mentioned redundant technique can be combined with the improved parity checking technique so as to be able not only to correct the previously determined hard errors but also to correct soft errors or hard errors caused after the determination of the previously determined hard errors. However, since the parity-checking two-dimensional virtual matrix has a predetermined logic for outputting data in response to a selected memory cell, it is impossible to simply replace a defective column with the redundant column. Therefore, unless a great number of circuit elements are used for preventing the previously determined hard errors from entering the two-dimensional virtual matrix, it is difficult to combine the redundant technique with the improved parity-checking technique.